In a nonvolatile electronic device of a flash memory, modify operations (word or buffered programming, sector or bank erasing) are managed by a microcontroller. Referring to FIG. 1, a microcontroller 100 drives several different blocks, including voltage generator (BLOCK GEN) 110, pumps, regulators, address and time counters, switches, etc., by executing instructions of an algorithm written in a program storage device 120, e.g., an embedded ROM (or SRAM), and setting opportune outputs, as is well understood in the art. The number of operations to execute is increased in a significant way in multilevel flash memories where each flash cell can assume more than two different physical states. Of course, not only a correct functionality of modify operations is required but also a low area cost of circuitry used and strong timing performances.
In multilevel memory, operations are very different depending upon the kind of modify made along with the amount of parallelism used. In previous devices, the different options used were fully managed by the microcontroller that executed different branches of the algorithm according to the operation made and the characteristic of such operation. The algorithm had to manage the appropriate increment to use, had to load start program values, had to control the slope of the modify, including those cases with changes at certain voltages, and the microcontroller also had to stop increments once the maximum voltage had been reached. As a result, the code becomes very long, taking up much memory space, without enough flexibility and ability to reuse it in different structures.
In addition to these difficulties, management is required for switching between modify pulses and verify voltages. In fact, many flash memory modify operations are characterized by the sequence: modify pulse (to modify the state of selected cells); verify cell condition (logic value associated); and modify pulse at a higher voltage (in the event of a verify fail). This sequence is repeated until the verify succeeds or a maximum number of attempts has been reached (i.e., a case of failed operation).
In single level memory programming, for instance, the pulse can be obtained by applying a ramp from 2V to 9V (volts) with a fixed slope (e.g., 1.5V/usec (microsecond)) on flash cell gates. After the program pulse, a verify occurs by a comparison of current between a cell that has to be programmed and a precisely set reference with a voltage at its gate equal to the gate voltage of the selected cell (Vverfify). Programming usually ends after one or two pulse-verify sequences. Consecutive pulse conditions are the same, i.e, each program pulse has exactly the same characteristics of other pulses. In this case, the algorithm alternatively sets values used for the programming pulse and the values used for the verify conditions. So when a verify fails, the algorithm loads into BLOCK GEN 110, the next digital pulse value that is always the same, and it is not important if the pulse is the first, the second, or the tenth pulse. The program pulse value is not dependent upon the pulse number, and this is easy to manage by the algorithm. Possible sequences 1000, 1010 used in single level memories are shown in FIGS. 10a and l0b. 
A completely different situation occurs in multilevel flash memory algorithms. In the case of program, for instance, each pulse has different conditions in order to have perfect control of the cells to be programmed. Usually, at each program pulse, following a verify operation, the gate voltage of the selected cells is 125 mV (millivolts) (SINGLE STEP) or 250 mV (DOUBLE STEP) higher than the previous pulse. So, when a verify occurs and the result is not successful, the circuitry or algorithm has to set the new pulse voltage in a way that depends on the previous attempt. This means that the pulse condition depends on the pulse number. It is possible to set a fixed voltage value which determines a slope change. Possible ramps for multilevel flash memory are shown in FIGS. 11a, 11b, 11c, and 11d. 
In FIG. 11a, a ramp 1100 is shown with a single step increment between pulses. FIG. 11b shows a ramp 1110 with a double step between pulses. A ramp 1120, with a slope change when a fixed voltage (CHANGE_RAMP_VOLT) is reached, is shown in FIG. 11c. In FIG. 11d, a blind ramp 1130 is shown, where a blind ramp refers to a ramp where no verify occurs between pulses and which is often used during test mode operations in multilevel devices. For FIGS. 11a, 11b, and 11c, these ramp illustrate situations with a pulse duration of Tpulse (where the time is counted in a flash counter) and intermediate verifies.
A typical approach used for an algorithm for prior art structures to obtain a ramp of pulses with intermediate values (e.g., the ramp of FIG. 11c) includes:
1. Load the first pulse digital value into a counter.
2. Provide a programming pulse.
3. Store the current pulse value in a register.
4. Load the verify configuration bits into the counter.
5. Execute a verify sequence.
6. Reload the last pulse digital value (if previous verify is not ok) from the register.
7. Determine if the maximum permitted voltage has been reached.
8. Determine if the voltage of slope changing has been reached.
9. Give none, one, or more increment(s) to set the next pulse digital value.
10. Provide a new programming pulse.
Steps 3 through 10 have to be executed in a loop until the verify operation is okay or the maximum number of attempts has been reached, in which case the operation fails.
A need exists for an approach that minimizes the control needed by the microcontroller while permitting faster management of pulse/verify and verify/pulse sequences during programming of flash memory cells. The present invention addresses such a need.